The invention relates to the field of electron beam lithography. More particularly, the invention relates to shaped beam lithography for generating patterns on photoresist for use in integrated circuit manufacturing processes.
According to prior art methods, an e-beam system's computer breaks a desired pattern into individual spots and then writes and stitches the spots together on a wafer or other substrate to generate a representation of the pattern, typically in a layer of photoresist layered on the substrate. In state of the art shaped electron beam systems, the individual spots can vary in size from a sliver (for example 0.1 .mu.m.times.2.0 .mu.m) to a square (for example 2.0 .mu.m.times.2.0 .mu.m). The shaping system on the e-beam column is calibrated so that the spot size on the target (wafer or other substrate) matches that which is desired. In practice, individual spots are written and positioned at a spatial period that matches the desired spot size. The gain of the shaping system is adjusted and the deflection system calibrated so that there is no gap or bulge in adjacent spots on exposed photoresist.
Referring now to FIG. 1, three examples of spot-to-spot stitching are presented according to the prior art. In the first example the e-beam system perfectly positions two spots 10. The pattern of exposed photoresist comprises two exposed spots 20 that match the desired pattern. In the second example, the e-beam system slightly mispositions two spots 12 with a small gap therebetween. This same gap would occur for correctly-positioned spots that were too small. The resulting pattern of exposed photoresist comprises two exposed spots 22 with a pair of indents 23. In the third example, the e-beam system slightly mispositions two spots 14 with a small overlap. The resulting pattern of exposed photoresist comprises two exposed spots 24 with a pair of cusps 25. These same cusps would occur for correctly-positioned spots that were too large. Electronic noise in either or both of the spot shaping electronics or the spot positioning electronics will make the gap or bulge between the spots variable, contributing to the linewidth variation.
Linewidth variation is an important factor in current integrated circuit design and fabrication. The acceptable variation in linewidth expressed as 3 .sigma. variation is generally about 10% of the minimum feature size written (e.g., 10 nm for 100 nm minimum feature size). Therefore, an electron beam lithography process that provides reduced linewidth variation is generally desired.